Computer Architecture with an Industrial RISC-V Core [RVfpga]
RISC-V, an open-standard computer architecture, is transforming processor design and software/hardware co-design, including enabling open source hardware implementations. This means that software development can occur alongside hardware development, accelerating the design process. Enroll today to develop your understanding of the RISC-V architecture and its ecosystem and get familiar with the RISC-V cores and system-on-chip.
Who Is It For :
This course is for junior level or higher university computer science, electrical and computer engineers and other technical students as well as others who would like to learn and experiment with RISC-V.
What You’ll Learn :
The course provides hands-on experience with RISC-V computer architecture and teaches how to develop and compile C and RISC-V assembly code for the RVFpga SoC as well as how to use and extend the input/output system of the RVfpga SoC. Additionally, you will learn how to configure the microarchitecture of the VeeR EH1 CoreTM and test its different features using performance counters and industry-standard benchmarks. Finally, the course provides step-by-step instructions on how to execute programs on the Nexys A7 board and simulate programs using: Whisper instruction set simulator (ISS); Verilator-based RVfpga-ViDBo; RVfpga-Pipeline; and RVfpga-Trace.
What It Prepares You For :
Upon completion, learners should be able to use RISC-V to improve security, power consumption and performance of processors and help shape the future of computer architecture.
- Online, Self Paced
- 20-40 Hours of Course Material
- Hands-on Labs & Assignments.
- 10 Weeks of Free Access to Online Course
- Optional Paid Certificate of Completion (verified track only)
- Discussion Forums
Details
- Chapter 1. Installation and Initial Demonstrations
- Chapter 2. C Programming with the RVfpga SoC
- Chapter 3. RISC-V Assembly Programming with the RVfpga SoC
- Chapter 4. RISC-V Function Calls
- Chapter 5. Mixing C and Assembly Functions in a Program
- Chapter 6. Introduction to Peripherals and Input/Output
- Chapter 7. More I/O: 7-Segment Displays
- Chapter 8. More I/O: Timers
- Chapter 9. Interrupts
- Chapter 10. Delving Deeper into the RISC-V VeeR Core
- Final Exam (verified track only)
Request more details
Schedules
Build skills with experts anytime, anywhere. Keep up to date with the latest trends in your industry. Explore all of our courses and pick your suitable ones to enroll and start learning!
Computer Architecture with an Industrial RISC-V Core
Hurry, Sale ends soon!
If you have any Queries about schedules Ask us here
More than 5 Participants ? Request for Corporate Training
Don't Miss Out On Amazing Benefits!
- Why Pay Higher For your Certification Courses when you can get them at much more competitive prices? Take the lowest-price challenge! Submit your Quote.
- Highest Rated For The Quality Training & Services
- 20000+ Certified Every year Through Meritglobal
- Avail Pay Later, EMI Options, Referral Bonus & More
